Researchers from the Massachusetts Institute of Technology have introduced a 36-core chip that features a “network-on-chip.” The chip solves one of the problems from previous attempts to design networks-on-chip: maintaining cache coherence. In today’s chips, all the cores are connected by a bus. When two cores need to communicate, they’re granted exclusive access to the bus, but that approach won’t work as the core count mounts. Cores will spend all their time waiting for the bus to free up. In a network-on-chip, each core is connected only to those immediately adjacent to it, which means there are multiple paths to a destination. A bus makes it easier to maintain cache coherence. To address this, the researchers equipped their chips with a second network, which shadows the first.
Source: MIT
